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July 2000 PRELIMINARY
ML4833* Electronic Dimming Ballast Controller
GENERAL DESCRIPTION
The ML4833 is a complete solution for a dimmable or a non-dimmable, high power factor, high efficiency electronic ballast. The BiCMOS ML4833 contains controllers for "boost" type power factor correction as well as for a dimming ballast. The ML4833 was designed to minimize the number of external components required to build an electronic ballast. The PFC circuit uses a new, simple PFC topology which requires only one loop for compensation. This system produces a power factor of better than 0.99 with low input current THD. An overvoltage protection comparator inhibits the PFC section in the event of a lamp out or lamp failure condition. The ballast controller section provides for programmable starting sequence with individually adjustable preheat and lamp out-of-socket interrupt times. The IC controls lamp output power through feedback. The ML4833 provides a power down input which reduces power to the lamp, for GFI, end of life, etc.
FEATURES
s s s s s s s s s s
Complete power factor correction and dimming ballast control in one IC Low distortion, high efficiency continuous boost, peak current sensing PFC section Programmable start scenario for rapid or instant start lamps Lamp current feedback for dimming control Variable frequency dimming and starting Programmable restart for lamp out condition to reduce ballast heating Internal over-temperature shutdown replaces external heat sensor PFC overvoltage comparator eliminates output "runaway" due to load removal Low start-up current <0.5mA Power reduction pin for end of life and GFI detectors (* Indicates part is End Of Life as of July 1, 2000)
BLOCK DIAGRAM
INTERRUPT 6 7 RSET RT /CT VARIABLE FREQUENCY OSCILLATOR OUTPUT DRIVERS RX/CX PRE-HEAT AND INTERRUPT TIMERS OUT A CONTROL & GATING LOGIC OUT B 3 PDWN 14 LAMP FB LFB OUT 8 4 5
9
13
PFC OUT
15
10 2 1 18
CRAMP PIFB PEAO PVFB/OVP POWER FACTOR CONTROLLER UNDER-VOLTAGE AND THERMAL SHUTDOWN PGND VCC VREF GND 12 16 17 11
1
ML4833
PIN CONFIGURATION
ML4833 18-Pin DIP (P18)
PEAO PIFB PDWN LAMP FB LFB OUT RSET RT/CT INTERRUPT RX/CX
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
ML4833 18-Pin SOIC (S18)
PVFB/OVP VREF VCC PFC OUT OUT A OUT B P GND GND CRAMP
PEAO PIFB PDWN LAMP FB LFB OUT RSET RT/CT INTERRUPT RX/CX 1 2 3 4 5 6 7 8 9 TOP VIEW 18 17 16 15 14 13 12 11 10 PVFB/OVP VREF VCC PFC OUT OUT A OUT B P GND GND CRAMP
TOP VIEW
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1 2
PEAO PIFB
PFC error amplifier output and compensation node. Sensing of the inductor current and peak current sense point of the PFC cycle by cycle current limit comparator. A one volt comparator threshold that switches the operating frequency to the preheat frequency when exceeded. Inverting input of an error amplifier used to sense (and regulate) lamp arc current. Also the input node for dimming control. Output of the lamp current error transconductance amplifier used for lamp current loop compensation. External resistor which sets oscillator FMAX, and R(X)/C(X) charging current. Oscillator timing components.
8
INTERRUPT Input used for lamp-out detection and restart. A voltage less than 1.25 volts resets the chip and causes a restart after a programmable interval. RX/CX Sets the timing for the preheat, dimming lockout, and interrupt. Integrated voltage of the error amp out. Ground. Power ground for the IC. Ballast MOSFET drive output. Ballast MOSFET drive output. Power Factor MOSFET drive output. Positive supply for the IC. Buffered output for the 7.5V voltage reference. Inverting input to PFC error amplifier and OVP comparator input.
9
3
PDWN
10 CRAMP 11 GND 12 P GND 13 OUT B 14 OUT A 15 PFC OUT 16 VCC 17 VREF 18 PVFB/OVP
4
LAMP FB
5
LFB OUT
6 7
RSET RT/CT
2
ML4833
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 60mA Output Current, Source or Sink (OUT A, OUT B, PFC OUT) DC ......................... 250mA Output Energy (capacitive load per cycle).............. 1.5 mJ Analog Inputs (LAMP FB, INTERRUPT, VCC) ........... -0.3V to VCC -2V PIFB input voltage ......................................... -1.5V to 2V Maximum Forced Voltage (PEAO, LFB OUT) ................................... -0.3V to 7.7V Maximum Forced Current (PEAO, LFB OUT) ........ 20mA Junction Temperature ............................................ 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering 10 sec.) .................... 260C Thermal Resistance (qJA) ML4833CP ...................................................... 70C/W ML4833CS .................................................... 100C/W
OPERATING CONDITIONS
Temperature Range ........................................ 0C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RSET = 22.1ky, RT = 15.8kW, CT = 1.5nF, CVCC = 1F, VCC = 12.5V. (Note 1)
PARAMETER Lamp Current Amplifier (LAMP FB, LFB OUT) Input Bias Current Small Signal Transconductance Input Voltage Range Output Low Output High Source Current Sink Current Voltage at LAMP FB = 3V, RL = Voltage at LAMP FB = 2V, RL = Voltage at LAMP FB = 0V, LFB OUT = 7V, TA = 25C Voltage at LAMP FB = 5V, LFB OUT = 0.3V, TA = 25C 7.1 -0.05 0.05 35 -0.3 0.2 7.5 -0.15 0.12 -0.3 65 -1.0 105 5.0 0.4 7.8 -0.25 0.22 A W V V V mA mA W CONDITIONS MIN TYP MAX UNITS
PFC Voltage Feedback Amplifier (PEAO, PVFB/OVP) Input Bias Current Small Signal Transconductance Input Voltage Range Output Low Output High Source Current Sink Current PFC Current -- Limit Comparator (PIFB) Current-Limit Threshold Propagation Delay Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Line, temperature 69 2.5 TA = 25C VCCZ - 4.5V < VCC 3
ML4833
ELECTRICAL CHARACTERISTICS
PARAMETER Oscillator (Continued) CT Charging Current Voltage at LAMP FB = 3V, RT/CT = 2.5V, RX/CX = 0.9V (Preheat) LAMP FB = 3V, RT/CT = 2.5V, RX/CX = Open CT Discharge Current Output Drive Deadtime Reference Section Output Voltage Line regulation Load regulation Temperature stability Total Variation Output Noise Voltage Long Term Stability Line, load, temp 10Hz to 10kHz TJ = 125C, 1000 hrs 7.35 50 5 TA = 25C, IO = 1mA VCCZ - 4.5V < VCC < VCCZ - 0.5V 1mA < IO < 5mA 7.4 7.5 2 2 0.4 7.65 7.6 35 15 V mV mV % V V mV Voltage at RT/CT = 2.5V -90 -180 4.0 0.65 -110 -220 5.5 1 -130 -260 7.0 1.35 A A mA s
(Continued)
CONDITIONS MIN TYP MAX UNITS
Preheat and Interrupt Timer (RX/CX where RX = 680ky, CX = 4.7F) Initial Preheat Period Subsequent Preheat Period Start Period Interrupt Period RX/CX Charging Current RX/CX Open Circuit Voltage RX/CX Maximum Voltage Input Bias Current Preheat Lower Threshold Preheat Upper Threshold Interrupt Recovery Threshold Start Period End Threshold Interrupt Input (INTERRUPT) Interrupt Threshold Input Bias Current RSET Voltage OVP Comparator (PVFB/OVP) OVP Threshold Hysteresis Propagation Delay 2.63 0.18 2.73 0.23 1.4 2.83 0.27 V V s 2.4 2.5 1.1 1.22 1.4 0.1 2.6 V A V Voltage at CRAMP = 1.2V 1.05 4.2 1.05 6.05 1.22 4.7 1.22 6.6 VCC < Start-up threshold -24 0.4 7.0 0.8 0.7 1.2 5.7 -28 0.7 7.3 -33 1.0 7.7 0.1 1.36 5.1 1.36 7.35 s s s s A V V A V V V V
4
ML4833
ELECTRICAL CHARACTERISTICS
PARAMETER Outputs (OUT A, OUT B, PFC OUT) Output Voltage Low IOUT = 20mA IOUT = 200mA Output Voltage High IOUT = -20mA IOUT = -200mA Output Voltage Low in UVLO Output Rise/Fall Time Under-Voltage Lockout and Bias Circuits IC Shunt Protection Voltage (VCCZ) Start-up Current Operating Current ICC = 15mA VCC - Start-up threshold VCC = 12.5V, Voltage at LAMP FB = 0V, LFB OUT = 2.3, PVFB/OVP = 2.3V PIFB = Open 14.2 15.0 0.34 5.5 15.8 0.48 8.0 V mA mA IOUT = 10mA, VCC < Start-up threshold CL = 1000pF 20 VCC - 0.2 VCC - 2.0 0.1 1.0 VCC - 0.1 VCC - 1.0 0.2 0.2 2.0 V V V V V ns
(Continued)
CONDITIONS MIN TYP MAX UNITS
Start-up Threshold Shutdown Threshold Shutdown Temperature (TDWN) Hysteresis (TDWN) PDWN PDWN Threshold
Note 1: Note 2: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. Junction temperature.
VCC - 1.2 VCCZ - 1.0 VCC - 0.8 VCC - 5.3 VCCZ - 4.8 VCC - 4.3 (Note 2) 130 30
V V C C
0.9
1.0
1.1
V
5
ML4833
FUNCTIONAL DESCRIPTION
OVERVIEW The ML4833 consists of peak current controlled continuous boost power factor front end section with a flexible ballast control section. Start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. The ballast section controls the lamp power using frequency modulation (FM) with additional programmability provided to adjust the VCO frequency range. This allows for the IC to be used with a variety of different output networks. Figure 1 depicts a detailed block diagram of ML4833. POWER FACTOR SECTION The ML4833 power factor section is a peak current sensing boost mode PFC control circuit in which only voltage loop compensation is needed. It is simpler than a conventional average current control method. It consists of a voltage error amplifier, a current sense amplifier (no compensation is needed), an integrator, a comparator, and a logic control block. In the boost topology, power factor correction is achieved by sensing the output voltage and the current flowing through the current sense resistor. Duty cycle control is achieved by comparing the integrated voltage signal of the error amplifier and the voltage across RSENSE. The duty cycle control timing is shown in Figure 2. Setting minimum input voltage for output regulation can be achieved by selecting CRAMP according to equation 1.
CRAMP = PEAOMAX 1 (1- D)Ts - 1.1s 22K 2P OUT - VOUT - 2VIN (1- D)Ts 8R SENSE 2L VIN
{
}
(1)
OVERVOLTAGE PROTECTION AND INHIBIT The OVP pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus sets the OVP trip level. When the voltage on PVFB/OVP exceeds 2.75V, the PFC transistor are inhibited. The ballast section will continue to operate.
6 7
RSET RT/CT OSC CLK + + - + - S 2.5V + V TO I - + - R Q 1.25V -
LFB OUT 2.5V LAMP FB INTERRUPT PDWN
5
9
RX/CX
4 8 3
PREHEAT TIMER
16 17 11
VCC VREF GND
UNDER-VOLTAGE THERMAL SHUTDOWN REFOK
1.0V
18 1 10
PVFB/OVP PEAO CRAMP
PFC OUT - 2.75V + OVP S R TQ -1.0V - + 2 PIFB ILIM OUT B PGND ISENSE AMPLIFIER Q OUT A
15
14
13 12
Figure 1. ML4833 Detailed Block Diagram
6
ML4833
TRANSCONDUCTANCE AMPLIFIERS The PFC voltage feedback amplifier is implemented as an operational transconductance amplifier. It is designed to have low small signal forward transconductance such that a large value of load resistor (R1) and a low value ceramic capacitor (<1F) can be used for AC coupling (C1) in the frequency compensation network. The compensation network shown in Figure 3 will introduce a zero and a pole at: fZ = 1 2 R1C1 fP = 1 2 R1C2 (2) Figure 3. Compensation Network
PVFB/OVP 18 2.5V - + R1 C2
C1
L
SW2 RA
VOUT
EMI FILTER RSENSE PIFB OUT A SINE -A + R - S SINE OSC RAMP V TO I + CLK VREF1 PEAO - CLK Q SW1 RB
INVERTER
LAMP NETWORK
L A M P L A M P
2
14
18
PVFB/OVP
PFC OUT 10 CRAMP R1 CRAMP C1 C2 1 PEAO
Figure 2. ML4833 PFC Controller Section
7
ML4833
Figure 4 shows the output configuration for the operational transconductance amplifiers. OSCILLATOR The VCO frequency ranges are controlled by the output of the LFB amplifier (RSET). As lamp current increases, LFB OUT falls in voltage, causing the CT charging current to increase, thereby causing the oscillator frequency to increase. Since the ballast output network attenuates high frequencies, the power to the lamp will be decreased.
CURRENT MIRROR IN OUT gmVIN 2 io = gmVIN
IQ + IQ - gmVIN 2
17
VREF ICHG
VREF CONTROL
RT
IN
OUT CURRENT MIRROR
CT 7
RT/CT 1.25/3.75
+ -
Figure 4. Output Configuration A DC path to ground or VCC at the output of the transconductance amplifiers will introduce an offset error. The magnitude of the offset voltage that will appear at the input is given by VOS = io/gm. For an io of 1A and a gm of 0.05 W the input referred offset will be 20mV. Capacitor C1 as shown in Figure 3 is used to block the DC current to minimize the adverse effect of offsets. Slew rate enhancement is incorporated into all of the operational transconductance amplifiers in the ML4833. This improves the recovery of the circuit in response to power up and transient conditions. The response to large signals will be somewhat non-linear as the transconductance amplifiers change from their low to high transconductance mode. This is illustrated in Figure 5.
iO
5.5mA
Figure 5. Transconductance Amplifier Characteristics BALLAST OUTPUT SECTION The IC controls output power to the lamps via frequency modulation with non-overlapping conduction. This means that both ballast output drivers will be low during the discharging time tDIS of the oscillator capacitor CT.
8
W
CLOCK
tDIS VTH = 3.75V
tCHG
CT VTL = 1.25V
Figure 6. Oscillator Block Diagram and Timing
VIN Differential Linear Slope Region
0
The oscillator frequency is determined by the following equations: FOSC = and
V + I R - VTL t CHG = R T CT In REF CH T VREF + ICH R T - VTH
1 t CHG + tDIS
(3)
(4)
The oscillator's minimum frequency is set when ICH = 0 where: FOSC 1 0.51x R T CT (5)
ML4833
This assumes that tCHG >> tDIS. When LFB OUT is high, ICH = 0 and the minimum frequency occurs. The charging current varies according to two control inputs to the oscillator: 1. The output of the preheat timer 2. The voltage at LFB OUT (lamp feedback amplifier output) In preheat condition, charging current is fixed at
TJ TA + (PD + 65C / W)
(9)
VCC VCCZ V(ON) V(OFF)
ICHG (PREHEAT) = 2.5 RSET
(6)
ICC 5.5mA
t
In running mode, charging current decreases as the voltage rises from 0V to VOH at the LAMP FB amplifier. The highest frequency will be attained when ICHG is highest, which is attained when voltage at LFB OUT is at 0V:
0.34mA t
ICHG(0) =
5 RSET
(7)
Highest lamp power, and lowest output frequency are attained when voltage at LFB OUT is at its maximum output voltage (VOH). In this condition, the minimum operating frequency of the ballast is set per equation 5 above. For the IC to be used effectively in dimming ballasts with higher Q output networks a larger CT value and lower RT value can be used, to yield a smaller frequency excursion over the control range (voltage at LFB OUT). The discharge current is set to 5mA. Assuming that IDIS >> IRT:
tDIS(VCO) 600 x CT
Figure 7. Typical VCC and ICC Waveforms when the ML4833 is Started with a Bleed Resistor from the Rectified AC Line and Bootstrapped from an Auxiliary Winding. STARTING, RE-START, PREHEAT AND INTERRUPT The lamp starting scenario implemented in the ML4833 is designed to maximize lamp life and minimize ballast heating during lamp out conditions. The circuit in Figure 8 controls the lamp starting scenarios: Filament preheat and lamp out interrupt. CX is charged with a current of IR(SET)/4 and discharged through RX. The voltage at CX is initialized to 0.7V (VBE) at power up. The time for CX to rise to 4.8V is the filament preheat time. During that time, the oscillator charging current (ICHG) is 2.5/RSET. This will produce a high frequency for filament preheat, but will not produce sufficient voltage to ignite the lamp or cause significant glow current. After cathode heating, the inverter frequency drops to FMIN causing a high voltage to appear to ignite the lamp. If lamp current is not detected when the lamp is supposed to have ignited, the lamp voltage feedback coming into pin 8 remains below 1.25V, the CX charging current is shut off and the inverter is inhibited until CX is discharged by RX to the 1.2V threshold. Shutting off the inverter in this manner prevents the inverter from generating excessive heat when the lamp fails to strike or is out of socket. Typically this time is set to be fairly long by choosing a large value of RX.
(8)
IC BIAS, UNDER-VOLTAGE LOCKOUT AND THERMAL SHUTDOWN The IC includes a shunt clamp which will limit the voltage at VCC to 15V (VCCZ). The IC should be fed with a current limited source, typically derived from the ballast transformer auxiliary winding. When VCC is below VCCZ - 1.1V, the IC draws less than 0.48mA of quiescent current and the outputs are off. This allows the IC to start using a "bleed resistor" from the rectified AC line. To help reduce ballast cost, the ML4833 includes a temperature sensor which will inhibit ballast operation if the IC's junction temperature exceeds 120C. In order to use this sensor in lieu of an external sensor, care should be taken when placing the IC to ensure that it is sensing temperature at the physically appropriate point in the ballast. The ML4833's die temperature can be estimated with the following equation:
9
ML4833
0.625 RSET RX/CX 9 CX RX 6.8 + 1.2/6.8 INTERRUPT 8 1.25V - + - R Q S DIMMING LOCKOUT INHIBIT 1.2/4.8 + HEAT -
A summary of the operating frequencies in the various operating modes is shown below. Operating Mode
Preheat Dimming Lock-out Dimming Control
Operating Frequency
[F(MAX) to F(MIN)] 2 F(MIN) F(MIN) to F(MAX)
TYPICAL APPLICATIONS
Figure 8. Lamp Preheat and Interrupt Timers LFB OUT is ignored by the oscillator until CX reaches 6.8V threshold. The lamps are therefore driven to full power and then dimmed. The CX pin is clamped to about 7.5V. Figure 10 shows a schematic for a dimming power-factor corrected 60W ballast, designed to operate two F32T8 fluorescent lamps connected in series.
6.8 4.8 RX/CX 1.2 .65 0 HEAT
DIMMING LOCKOUT
>1.25 INT
INHIBIT
Figure 9. Lamp Starting and Restart Timing
10
F1 TP4 D3 D1 6 R11 T1 C3 C2 D13 D9 C10 R13 C20 + R1 D12 D6 R20 D10 C22 C17 R14 C19 R10 R22 R19 18 17 16 15 14 13 12 11 10 R24 D11 TP2 R16 C8 TP5 1 5 T5 10 6 TP1 8 6 7 1 R8 3 2 1 9 8 C9 B R7 R18 T4 4 C23 R Y Y B Q3 R D5 C26 C25 Q1 7 2 R12 L2 D4 D2 R6 6 3 9 8 T2 D7 R17 Q2 10 C1 D8
L1
HOT
220 VAC
NEUTRAL
1 2 3 4 5 6 7 R25 9
RXCX CRAMP INTERRUPT GND RSET RTC T PGND OUT B LFB OUT OUT A LAMP FB PFC OUT PDWN VCC PIFB PEAO PVFB
ML4833 U1
VREF
PDWN
R4
Figure 10. 220V Dimming Ballast
R3 R2 8 C7 C11 C6 R15 R5 C5 TP3 C4 R23 C14 C13 C15 C12 C16 D1 R6 Q1 4 D2 3 C1 R7 C4 C2 5 R4 DIMMER CONTROL INTERFACE SUBASSEMBLY 6 R8 R1 R5 C3 R3 3 2 + - U2 + - 4 7 8 1 R2
C24
R21
C21
T1
U1
VIOLET GRAY
ML4833
REMOTE MANUAL DIMMER 0-10VDC
11
ML4833
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P18 18-Pin PDIP
0.890 - 0.910 (22.60 - 23.12) 18
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.045 MIN (1.14 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S18 18-Pin SOIC
0.449 - 0.463 (11.40 - 11.76) 18
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
12
ML4833
ORDERING INFORMATION
PART NUMBER ML4833CP (End of Life) ML4833CS (Obsolete) TEMPERATURE RANGE 0C to 85C 0C to 85C PACKAGE Molded DIP (P18) SOIC (S18)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4833-01
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